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EPM9560ARC208-10N

Part Number: EPM9560ARC208-10N

Link to Datasheet

Manufacturer: Altera

Quantity Available: 2628

Lifecycle: NRND

MSL: 3

Package Description:

Pin Count: 208

Mounting Type: Surface Mount

ECCN: 3A991

Schedule B: 8542390000

RoHS: Compliant

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About The Altera EPM9560ARC208-10N

The MAX 9000 family which is associated with in-system-programmable, high performance and high-density EPLDs are all based on the Altera’s 3rd generation MAX architecture. This is fabricated on the advanced CMOS technology, EEPROM-based MAX 9000 family offers from 6,000 up to 12,000 usable gates along with pin-to-pin delays which reach up to speeds of 10ns, and the counter-speeds that can reach up to 144 MHz. Their 10-speed grade associated with the MAX family happens to be compliant with a PCI Local Bus.

Specification- Revision 2.2

The MAX 9000 features an architecture that supports integration of high-density for the system-level logical functions. It can easily integrate a number of programmable-logic devices that range from, 22V10s, GALs, PALs onto FPGA (field programmable gate array) devices along with EPLDs.

All the MAX 9000 device packages offer 4 dedicated-inputs in relation to global-control signals along with large fan-outs. Each of the I/O pins has a linked I/O cell-register that features clock-enable controls on the actual periphery of these devices. In the form of outputs, the registers offer quick clock-to-output times and in the form of inputs, they provide fast setup times.

MAX 9000 EPLDs offer 5.0-V ISP (in-system programmability). This is the features that provide a way for the device to be reprogrammed or programmed on the PCB (printed circuit board) for efficient and fast iterations during the debug cycles and design development. The MAX 9000 devices have been guaranteed for up to 100 erase and program cycles.

MAX 9000 EPLDs contain between 320 to 560 macrocells which are combined into groups made up of 16 macrocells, known as LABs (logic array blocks). Each of the macrocell features a programmable or fixed array along with a register that is configurable along with an independent programmable clock, clear, clock enable along with preset functions. To provide increased flexibility, the macrocells each offer dual-output structures that provide the product-terms and register that are all used independently.

This is the feature that provides combinatorial-intensive and register-rich designs that are implemented with efficiency. Dual-output structures of the MAX 9000 macrocell improve on logic utilization, which therefore increases effective capacity of these devices. In order to build a complex-logic function, every macrocell is able to be supplemented with “high-speed expander product terms” and “shareable expander product terms” that are able to offer up to a maximum of 32 product terms for each macrocell.

The MAX 9000 family offers programmable power or speed optimization. The speed-critical parts of this design are able to run efficiently at full power or high speed, while remaining parts will run at decreased low power or low speed. This power/speed combination feature allows for a user to configure either 1 or more of the macrocells in order to operate at around 50% or less speed or power while adding only a small nominal time delay.

The MAX 9000 devices also offer the choice to reduce slew rates in regards to the output-buffers, which minimizes the noise transients while the non-speed-critical signal switch over. MAX 9000 devices provide a MultiVolt feature that allows the output-drivers a way to be set for 3.3V or 5.0-V operation inside mixed-voltage systems.