As you can see in Figure 2, the CLBs shape a central logic structure with simple access to all help and directing structures. The IOBs are situated around all the logic and memory components for simple and fast steering of all signals both on and off this chip
The values put into the static memory cells can control all of the adjustable logic components and interconnect assets.
These values stack into the memory cells when the device is powered on, and can reload if important to change the capacity of the gadget.
Each of these components will be examined in detail in the following discussions.
Input and Output Block
The Spartan-II FPGA IOB, as observed in Figure 2, has inputs and outputs which can be used with a wide assortment of I/O standards. These rapid I/Os are equipped to support many different state-of-the-art bus and memory interfaces.
Table 3 has a few of the standards supported alongside the reference, termination and output voltages required to meet these standards.