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XC2S200-5FG456C

Part Number: XC2S200-5FG456C

Link to Datasheet

Manufacturer: Xilinx

Quantity Available: 4076

Lifecycle: NRND

MSL: 3

Package Description: Fine Pitch Ball Grid Array

Pin Count: 456

Mounting Type: Surface Mount

ECCN: 3A991.d

Schedule B: 8542390000

RoHS: Not Compliant

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Specifications for the Xilinx XC2S200-5FG456C

Description of Architecture

The Spartan II FPGA Array

-II field-programmable gateway array, appearing in Figure 2, is made out of five noteworthy configurable components:

  • IOBs provide an interface between package pins and internal logic
  • CLBs give the useful components to developing the majority of logic elements
  • Committed block RAM of 4096 bits
  • Clock DLLs for clock-dissemination defer compensation and allow domain control
  • Adaptable multi-level interconnect structure

As you can see in Figure 2, the CLBs shape a central logic structure with simple access to all help and directing structures. The IOBs are situated around all the logic and memory components for simple and fast steering of all signals both on and off this chip

The values put into the static memory cells can control all of the adjustable logic components and interconnect assets.
These values stack into the memory cells when the device is powered on, and can reload if important to change the capacity of the gadget.

Each of these components will be examined in detail in the following discussions.

Input and Output Block

The Spartan-II FPGA IOB, as observed in Figure 2, has inputs and outputs which can be used with a wide assortment of I/O standards. These rapid I/Os are equipped to support many different state-of-the-art bus and memory interfaces.
Table 3 has a few of the standards supported alongside the reference, termination and output voltages required to meet these standards.

The three IOB registers work either as edge-triggered level-sensitive latches or D type flip-flops. Every IOB has a clock signal or CLK which is shared by all of the 3 registers and free Clock Enable (CE) signals for each of these registers. The three registers also share a Set/Reset or SR.
For each register, this flag can be freely arranged as an asynchronous Preset, a synchronous Set, a synchronous Reset, an offbeat Preset, or an asynchronous Clear.
A component not appearing in the diagram, but that is controlled by the product, is the polarity control. Both the input and the output buffers and the majority of the IOB control signals have separate and independent polarity controllers.