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XC2S200-6PQG208C

Part Number: XC2S200-6PQG208C

Link to Datasheet

Manufacturer: Xilinx

Quantity Available: 2529

Lifecycle: NRND

MSL: 3

Package Description: Plastic Quad Flat Package

Pin Count: 208

Mounting Type: Surface Mount

ECCN: EAR99

Schedule B: 8542390000

RoHS: Compliant

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Xilinx XC2S200-6PQG208C

Input Path

The Spartan II IOB input path features a buffer which directs the signal to internal logic. Optionally, it might pass through an input flip-flop.
The D-input of the flip-flop has an optional delay element which eliminates pad-to-pad hold time. This delay is equal to the one of the internal clock-distribution of the board. When this function is used, it sets the pad-to-pad time to zero.
The input buffers can be configured in according to any of the low-voltage standards supported. In some situations the input buffer has a threshold voltage supplied by the user, known as V REF.

As the V REF value has to be supplied by the user, it triggers constraints on which standards can actually be used together. You can find more details on this issue in the I/O Banking section.Once the configuration is done, you can use the optional pull-up and pull-down resistors located at each input.

Output Path

The output path consists from a 3-state output buffer which conducts the output signal. This signal can either be routed directly or through an IOB flip-flop.
This applies also to the output signal, which can be routed either directly or through a flip-flop with synchronous enable and disable.

Each output driver can be programmed for a specific low-voltage signaling standard. The output drivers can source up to 24 mA and sink up to 48 mA. The slew rate controls and the drive strength allow the minimization of bus transients.
Most signaling standards link the output high voltage to an externally supplied V CCO voltage. This requirement to supply V CCO voltage limits the range of standards that can be jointly used. See the I/O Bank section for further information on this issue.

Each output is connected to a weak-keeper circuit. These circuits are optional. When the are selected, they monitor the voltage on the pad, while also driving the pin High or Low for matching the input signal. When the pin is connected to a signal coming from multiple sources, the weak keeper makes sure the signal is maintained in its last state if all drivers are disabled. This is a very effective way of eliminating bus chatter.
As the weak-keeper circuit requires the use of the IOB input buffer for monitoring the input level, the right V REF voltage has to be provided if required by the signaling standard. This voltage has to comply with the I/O banking.