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Part Number: XC2S50-5FGG456C

Link to Datasheet

Manufacturer: Xilinx

Quantity Available: 2439

Lifecycle: NRND

MSL: 3

Package Description: Fine Pitch Ball Grid Array

Pin Count: 456

Mounting Type: Surface Mount


Schedule B: 8542390000

RoHS: Compliant

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The XC2S50-5FGG456C From Xilinx


The Spartan-II FPGAs contain Configurable Logic Blocks that have a programmable feature built in an ordinary, but flexible perimeter of input and output blocks. These have four corners with DLLS or delay-locked loops. One is at each corner of the die with there being two columns of RAM blocks on opposite sides of it between the configurable logic blocks and the input and output blocks.

These are functional elements which are also connected together in a strong hierarchy of movable routing channels as illustrated in Figure 1.

Customize the Spartan-II by loading your chosen configuration into the FPGA’s static memory cells. These can be reprogrammed an unlimited number of times when programmed in this manner. The stored values in the cells will determine the logic and interconnections within the FPGA.

Read the configuration information from the external serial PROM when at the master serial mode. You can also see it within the FPGA’s slave serial-parallel or the boundary scan.

This brand of FPGA is used in high-volume applications. It allows for a fast reprogramming which can make it beneficial in many different situations. You can shorten your product development cycles with it while also enjoying a cost-effective method of producing mass quantities of those products.

Spartan-II FPGAs make use of their high-tech architecture and their semiconductor technology to make these high-performance lower cost applications. The system clock can rate up to 200 MHz, and besides having the benefit of programmable logic, it also has an on-chip sync in both single and dual port RAM. It includes both block and distributed forms. Additional features include the programmable set and reset, fast-carry logic and DLL clock drivers.

Spartan-II FPGA Array is a field programmable gate array as illustrated in Figure 2. It has five main elements which can be configured:

  • IOBs to provide the interface between the internal logic and package pins
  • CLBs that provide the functional elements for constructing logic
  • Dedicated block RAMs have 4096 bits of memory
  • Multi-level interconnecting structure
  • Clock DLLs provide clock domain control and clock-distribution delay compensation